1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to the formation of ultra shallow extensions in transistor devices.
2. Description of the Related Art
In attempting to increase the performance of modem transistor devices, all potential sources of performance degradation must be addressed. One such area of performance degradation in such devices is the parasitic capacitances that occur when the extensions of typical source/drain regions extend under the gate dielectric of modem devices. These parasitic capacitances must be charged and discharged during every on/off cycle of a typical transistor. While this charging and discharging of these capacitances occurs relatively rapidly, the charging and discharging does take a finite period of time, which acts to slow down the operation of the transistor.
By way of background, a typical field effect transistor is comprised of a gate dielectric positioned above a silicon substrate, a gate conductor positioned above the gate dielectric, and a plurality of source/drain regions that are self-aligned to the gate dielectric. The source/drain regions are typically created by one or more ion implantation processes in which the appropriate dopant material, e.g., arsenic for NMOS technology, is implanted into the silicon substrate. After this initial implantation process, the implanted region is subjected to a heating operation to activate the dopant, i.e., to realign the lattice structure such that the dopant atoms are substitutionally placed within the polysilicon and silicon structure. Typically, this heating process may be a rapid thermal anneal (RTA) process performed at a temperature of 950-1100.degree. C. for a 5-20 seconds. This heat treating process causes an aniso-tropic spreading of the previously implanted dopant materials in the substrate, i.e., the dopant spreads under the gate as well as into the substrate. The spreading of the dopant material under the gate dielectric may create a parasitic capacitance that acts to degrade the performance of the transistor device.
The present invention is directed to a method and apparatus for solving, or at least reducing the effects of, some or all of the aforementioned problems.